CALL FOR PAPERS

This Workshop explores emerging trends and novel concepts in the area of VLSI. The theme of the Workshop is System Design for a System-on-Chip Era. System Level Design has been identified as a dominant research theme for the next decade. System Design has been gaining significance and momentum recently due to the emergence of system-on-a-chip designs. New visionary approaches at the system design level are needed to exploit the great opportunities created by the continuous advances in technology and miniaturization of the semiconductor devices. System design is converging on a paradigm which includes general purpose commodity chips (i.e. processors, memories, DSP) and full custom mixed analogy and digital application specific integrated circuits (ASICs) integrated via programmable gate arrays on custom printed circuit boards or complete silicon boards, System-on-a-Chip. These hardware systems will be driven by custom, real time software that utilizes the latest software design paradigms (i.e. object oriented languages, client-server architecture, browser interfaces) and wireless communications to provide users with unique functionality - either stand-alone or in collaboration with other geographically distributed users. To be effective, these systems must be optimized taking into account a variety of constraints including complexity, power consumption, heat dissipation, mechanical packaging, ergonomics, and design effort. Only recently have multi-disciplinary teams begun concurrent design where-in the effect of interactions between trade-offs within disciplines is becoming apparent. Such trade-offs are not yet supported by CAD tools. Future system design methodologies will be one of the key topics at the Workshop. Contributions are sought in all areas related to the system level design, including but not limited to:

Emerging Trends in VLSI
System Design and System-on-a-Chip Design Methods
Application-Specific Low Power VLSI System Design
System Issues in Complexity, Low Power, Heat Dissipation
Design Frameworks for System Design
System Test and Verification
Design for Testability
Intellectual property creating and sharing
System-on-a-chip IP Issues
Mixed-Signal Design
Electrical/Mechanical/Software Co-Design
Complete University System Design Projects
Industrial Approaches to System Design

PARTICIPATION

The Workshop Program will include contributed papers and speakers invited by the Program Committee. Attendance at the Workshop is limited to 100 persons to encourage interaction. The keynote addresses, and a banquet are planned besides the technical sessions.

PAPER SUBMISSION AND DEADLINES

Authors should send five copies of their manuscripts to:

Asim Smailagic
Carnegie Mellon University
ICES
Hamburg Hall
Pittsburgh, PA 15213, USA

Electronic submission is strongly encouraged. Submissions should be no more than ten pages long. The cover page should include (1) title, (2) authors and affiliation, (3) e-mail address of the contact author, (4) an abstract describing the contributions, and (5) body of the paper. Due dates are:

December 15, 1999 - Manuscript max ten pages
January 15, 2000 - Notification of acceptance
February 15, 2000 - Final paper for the Proceedings

WORKSHOP REGISTRATION

The registration fee includes two lunches, banquet, coffee breaks and workshop fees. The registration form will be made available along with the advance program during February 1999. Advance registration will be available till February 28, 2000.