Peer-Reviewed Journal Articles

1. H. Sankaran and S. Katkoori, "Simultaneous Scheduling, Allocation, Binding, Re-ordering, and Encoding for Crosstalk Pattern Minimization during High Level Synthesis," To appear in IEEE Transactions on VLSI Systems.
   
   
2. V. Krishnan and S. Katkoori, "TABS: Temperature-Aware Layout Driven Behavioral Synthesis," To appear in IEEE Transactions on VLSI Systems.
   
   
3. P. Fernando and S. Katkoori, D. Keymeulen, R. Zebulum, and A. Stoica, "A Customizable FPGA IP Core Implementation of a General Purpose Genetic Algorithm Engine," To appear in IEEE Transactions on Evolutionary Computation.
   
   
4. S. Roy, N. Ranganathan, and S. Katkoori, "A Framework For Power-Gating Functional Units in Embedded Microprocessors," IEEE Transactions on VLSI Systems, Volume 17, Issue 11, Nov. 2009 Page(s):1640 - 1649.
   
   
5. K. Vyas and S. Katkoori, "A Genetic Algorithm for Design Space Exploration of Datapaths during High Level Synthesis," IEEE Transactions on Evolutionary Computation, Volume 10, Issue 3, June 2006 Page(s):213 - 229.
   
   
6. S. Gupta and S. Katkoori, "Intra Bus Crosstalk Estimation Using Word-Level Statistics," IEEE Transactions on Computer-Aided Design of ICs and Systems, Volume 24, Issue 3, March 2005 Page(s):469 - 478.
   
   
7. P. K. Samudrala, J. Ramos, and S. Katkoori, "Selective Triple Modular Redundancy (STMR) Based Single Event Upset (SEU) Tolerant Synthesis for FPGAs," IEEE Transactions on Nuclear Science, Volume: 51 , Issue: 5 , Oct. 2004, Pages: 2957-2969.
   
   
8. S. Alupoaei and S. Katkoori, "Ant Colony System Application for Macrocell Overlap Removal," IEEE Transactions on VLSI Systems, Volume: 12 , Issue: 10 , Oct. 2004 Pages:1118 - 1123.
   
   
9. S. Alupoaei and S. Katkoori, "Net Clustering Based Constructive and Iterative Improvement Approaches for Macro-cell Placement," Journal on VLSI Signal Processing, Vol. 37, No. 1, May 2004, pp. 151-163.
   
   
10. H. Li, W. K. Mak, and S. Katkoori, "Power Minimization Algorithms for LUT Based FPGA Technology Mapping," ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 9, No. 1, January 2004, pp. 33-51.
    
    
11. C. Gopalakrishnan, S. Katkoori, and S. Gupta, "Power Optimization Using Input-based Transformations," Vol. 150, No. 3, May 2003, IEE Proceedings - Computers and Digital Techniques, pp. 133-142.
    
    
12. S. Alupoaei and S. Katkoori, "Net-Based Force-directed Macrocell Placement for Wirelength Optimization," IEEE Transactions on VLSI Systems, Vol. 10, No. 6, December 2002, pp. 824- 835.
    
    
13. R. Vemuri, S. Katkoori, M. Kaul, and J. Roy, "An Efficient Hierarchical Register Optimization Algorithm for High Level Synthesis from Behavioral Specications," ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 7, No. 1, January 2002.
    
    
14. S. Katkoori and R. Vemuri, "Architectural Power Estimation Based on Behavioral Level Profiling," pp. 255-270, Vol.7, No. 3, Journal on VLSI Design, 1998.
    
    
15. N. Kumar, S. Katkoori, L. Rader and R. Vemuri, "Profile-Driven Behavioral Synthesis for Low Power VLSI Systems," IEEE Design & Test of Computers, Fall Issue, pp.70-84, 1995.
    
    

Peer-Reviewed Conference Papers

1. S. Roy, N. Ranganathan, and S. Katkoori, "Compiler Directed Power Gating in Embedded Micro-processors," IEEE International Conference on Computer Design (ICCD), October 2009, Page(s): 35-40.
   
   
2. S. Roy, N. Ranganathan, and S.Katkoori, "Exploration of Compiler Optimization Techniques for Enhancing Power Gating," IEEE International Symposium on Circuits and Systems (ISCAS), May 2009, Page(s): 1004-1007.
   
   
3. H. Sankaran and S. Katkoori, "Floorplan Driven High Level Synthesis for Crosstalk Noise Minimization in Macro-cell Based Designs," IEEECS Annual Symposium on VLSI (ISVLSI), May 2009, Page(s): 274 - 279.
   
   
4. H. Sankaran and S. Katkoori, "On-chip Dynamic Worst-case Crosstalk Pattern Detection and Elimination for Bus-based Macro-cell Designs," International Symposium on Quality Electronic Design (ISQED), March 2009, Page(s): 33 - 39.
   
   
5. V. Krishnan and S. Katkoori, "Simultaneous Peak Temperature and Average Power Minimization during Behavioral Synthesis," 22nd International Conference on VLSI Design (VLSID), January 2009, Page(s): 419 - 424.
   
   
6. H. Sankaran and S. Katkoori, "Simultaneous Scheduling, Allocation, Binding, Re-ordering, and Encoding for Crosstalk Pattern Minimization during High Level Synthesis," IEEE Computer Society Annual Symposium on VLSI (ISVLSI), April 2008, Page(s): 423 - 428.
   
   
7. H. Sankaran and S. Katkoori, "Bus Binding, Re-ordering, and Encoding for Crosstalk-producing Switching Activity Minimization during High Level Synthesis," 4th IEEE Symposium on Electronic Design, Test, and Applications (DELTA), January 2008, Page(s): 454 - 457.
   
   
8. P. Fernando, H. Sankaran, S. Katkoori, D. Keymeulen, A. Stoica, R. Zebulum, R. Ramesham "A Customizable FPGA IP Core Implementation of a General-Purpose Genetic Algorithm Engine," IEEE International Symposium on Parallel and Distributed Processing (IPDPS) 2008, April 2008, Page(s): 1 - 8.
   
   
9. V. Krishnan and S. Katkoori, "A 3D-Layout Aware Binding Algorithm for High-Level Synthesis of Three-Dimensional Integrated Circuits," 8th International Symposium on Quality Electronic Design (ISQED), March 2007, Page(s): 885-892.
   
   
10. V. Krishnan and S. Katkoori, "Minimizing wire delays by net-topology aware binding during Floorplan- driven high level synthesis," 2007 IFIP International Conference on Very Large Scale Integration (VLSI-SOC), October 2007, Page(s):99-104.
    
    
11. P. Fernando and S. Katkoori, "An Elitist Non-Dominated Sorting Based Genetic Algorithm for Simultaneous Area and Wirelength Minimization in VLSI Floorplanning," 21st International Conference on VLSI Design (VLSID), January 2008, Page(s): 337 - 342.
    
    
12. V. Krishnan and S. Katkoori "Clock Period Minimization with Iterative Binding Based on Stochastic Wirelength Estimation during High-Level Synthesis," 21st International Conference on VLSI Design (VLSID), January 2008, Page(s): 641 - 646.
    
    
13. A. Stoica, R. Zebulum, D. Keymeulen, R. Ramesham, J. Ne, and S. Katkoori, "Temperature-Adaptive Circuits on Recongurable Analog Arrays," IEEE Aerospace Conference, March 2007, Page(s): 1 - 6. (No hardcopy proceedings.)
    
    
14. D. Keymeulen, R. Zebulum, R. Rajeshuni, A. Stoica, S. Katkoori, S. Graves, F. Novak, and C. Antill, "Extreme Temperature Electronics based on Self-Adaptive System using Field Pro-grammable Gate Array," IEEE Aerospace Conference, March 2007, Page(s):1 - 6. (No hardcopy proceedings.)
    
    
15. W. Alvis, W.; S. Murthy, K. Valavanis, W. Moreno, M. Fields, and S. Katkoori, "FPGA based Flexible autopilot platform for unmanned systems," 2007 Mediterranean Conference on Control & Automation (MED), June, 2007, Page(s): 1 - 9.
    
    
16. S. Roy, S. Katkoori, and N. Ranganathan, "A Compiler Based Leakage Reduction Technique by Power-Gating Functional Units in Embedded Microprocessors," 20th International Conference on VLSI Design (VLSID), January 2007, Page(s): 215-220.
    
    
17. D. Keymeulen, R. Zebulum, R. Rajeshuni, A. Stoica, S. Katkoori, S. Graves, F. Novak, and C. Antill, "Self-Adaptive System Based on Field Programmable Gate Array for Extreme Temperature Electronics," First NASA/ESA Conference on Adaptive Hardware and Systems (AHS), June 2006 Page(s):296 - 300.
    
    
18. A. Stoica, R. S. Zebulum, D. Keymeulen, R. Ramesham, J. Ne, and S. Katkoori, "Temperature-Adaptive Circuits on Recongurable Analog Arrays," First NASA/ESA Conference on Adaptive Hardware and Systems (AHS), June 2006 Page(s):28 - 31.
    
    
19. V. Krishnan and S. Katkoori, "Design Space Exploration of RTL Datapaths using Rent Parameter based Stochastic Wirelength Estimation," 7th International Symposium on Quality Electronic Design (ISQED), March 2006, Page(s): 363 - 369.
    
    
20. R. Gopalan, C. Gopalakrishnan, and S. Katkoori, "Leakage Power Driven Behavioral Synthesis of Pipelined Datapaths," IEEE Computer Society Annual Symposium on VLSI (ISVLSI), May 2005, Page(s):167 - 172.
    
    
21. H. Sankaran, S. Katkoori, and U. Kailasam, "System Level Energy Optimization for Location- Aware Computing," IEEE Conference on Pervasive Computing (PerCom), March 2005, Page(s):319- 323.
    
    
22. H. Li, S. Katkoori, and Z. Liu, "Feedback Driven High Level Synthesis for Performance Optimization," 6th International Conference On ASIC (ASICON), Volume 2, October 2005, Page(s): 961 - 964.
    
    
23. H. Li, S. Katkoori, and W-K. Mak, "Force-Directed Performance Driven Placement Algorithm for FPGAs," Proceedings of IEEE Computer society Annual Symposium on VLSI (ISVLSI), February 2004, Page(s):193 - 198.
    
    
24. C. Gopalakrishnan and S. Katkoori, "Tabu Search Based Behavioral Synthesis of Low Leakage Datapaths," IEEE Computer society Annual Symposium on VLSI (ISVLSI), February 2004, Page(s): 260 - 261.
    
    
25. S. Gupta and S. Katkoori, "A Fast Word-Level Estimation Technique for Intra-Crosstalk," Design, Automation and Test in Europe (DATE) Conference, Volume 2, February 2004, Page(s): 1110-1115.
    
    
26. S. Alupoaei and S. Katkoori, "Energy Model Based Macrocell Placement for Wirelength Minimization," Proceedings of 17th International Conference on VLSI Design (VLSID), January 2004, Page(s): 713 - 716.
    
    
27. S. Alupoaei and S. Katkoori, "Ant Colony Optimization Technique for Macrocell Overlap Removal," Proceedings of 17th International Conference on VLSI Design (VLSID), January 2004, Page(s): 963 - 968.
    
    
28. S. Gupta and S. Katkoori, "Intra-Bus Crosstalk Estimation Using Word-Level Statistics," Proceedings of 17th International Conference on VLSI Design (VLSID), January 2004, Page(s): 449- 454.
    
    
29. C. Gopalakrishnan and S. Katkoori, "KnapBind: An Area-Ecient Binding Algorithm for Low-leakage Datapaths," Proceedings of 21st International Conference on Computer Design (ICCD), October 2003, Page(s): 430 - 435.
    
    
30. C. Gopalakrishnan and S. Katkoori, "A Fast Hierarchical Leakage Power Simulator for VHDL Structural Descriptions," IEEE Computer Society Symposium on VLSI (ISVLSI), February 2003, Page(s): 211-212.
    
    
31. H. Li, W. K. Mak, and S. Katkoori, "An Ecient LUT-Based FPGA Technology Mapping Algorithm for Power Minimization," Asia-Pacific Design Automation Conference (ASPDAC), January 2003, Page(s): 353-358. Nominated for Best Paper Award.
    
    
32. C. Gopalakrishnan and S. Katkoori, "Resource Allocation and Binding for Low Leakage Power," 16th International Conference on VLSI Design (VLSID), January 2003, Page(s): 297-302.
    
    
33. C. Gopalakrishnan and S. Katkoori, "Behavioral Synthesis of Datapaths with Low Leakage Power," IEEE International Symposium on Circuits and Systems (ISCAS), Volume: 4, May 2002, Page(s): 699 -702.
    
    
34. S. Gupta and S. Katkoori, "Force-directed Scheduling for Dynamic Power Optimization," IEEE Computer Society Annual Symposium on VLSI (ISVLSI), April 2002, Page(s): 68-73.
    
    
35. C. Gopalakrishnan and S. Katkoori, "Power Optimization using Input Transformations," First IEEE Intl. Workshop on Electronic Design, Test, & Applications (DELTA), January 2002, Page(s): 154-158.
    
    
36. S. Alupoaei and S. Katkoori, "Net Clustering Based Macro-cell Placement," 15th International Conference on VLSI Design (VLSID), January 2002, Page(s): 399-404.
    
    
37. H. Li, W. K. Mak, S. Katkoori, "Low Power Mapping for FPGAs with Optimal Depth," IEEE Computer Society Workshop on VLSI (WVLSI), April 2001, Page(s): 123-128.
    
    
38. S. Katkoori and S. Alupoaei, "RT-level Interconnect Optimization in DSM Regime," IEEE Computer Society Workshop on VLSI (WVLSI), April 2000, Page(s): 143-148.
    
    
39. S. Katkoori and R. Vemuri, "Scheduling for Low Power under Resource and Latency Constraints," International Symposium on Circuits and Systems (ISCAS), May 2000, Vol. 2, Page(s): 53-56.
    
    
40. A. Durbha and S. Katkoori, "Route-and-Place Design Methodology for Interconnect Optimization in DSM Regime," X IFIP International Conference on Very Large Scale Integration (IFIP VLSI), December 1999, Page(s): 427-438.
    
    
41. P. Maurer, S. Katkoori, W. Mak, M. Varanasi, "Component-Level Programming: A Revolution in Software Technology," Proceedings of the Frontiers in Education Conference, Proceedings of the 29th Annual Frontiers in Education Conference, Volume 2, November 1999, Page(s): 12B1/11-12B1/15.
    
    
42. S. Katkoori and R. Vemuri, "Accurate Resource Estimation Algorithms for Behavioral Synthesis," Great Lakes Symposium on VLSI Conference (GLSVLSI), March 1999, Page(s): 338-339.
    
    
43. V. Natesan, A. Gupta, S. Katkoori, D. Bhatia, and R. Vemuri, "A Constructive Method for Data Path Area Estimation During High-Level VLSI Synthesis," Asia and South-Pacific Design Automation Conference (ASPDAC), January 1997, Page(s): 509 - 515.
    
    
44. S. Katkoori and R. Vemuri, "Simulation Based Architectural Power Estimation for PLA-Based Controllers," International Symposium on Low Power and Electronic Design (ISLPED), August 1996, Page(s): 121-124.
    
    
45. S. Katkoori, J. Roy, and R. Vemuri, "A Hierarchical Register Optimization Algorithm for Behavioral Synthesis," 9th International Conference on VLSI Design (VLSID), January 1996, Page(s): 126-134.
    
    
46. S. Katkoori and R. Vemuri, "A Power Simulator for VHDL Structural Descriptions," VHDL International User's Forum (VIUF) Fall Conference, October 1995, Page(s): 4.17-4.25.
    
    
47. S. Katkoori, N. Kumar and R. Vemuri, "High Level Profiling Based Low Power Synthesis Technique," International Conference on Computer Design (ICCD), October 1995, Page(s): 446-452.
    
    
48. S. Katkoori, N. Kumar, L. Rader and R. Vemuri, "A Profile Driven Approach for Low Power Synthesis," IFIP Intl. Conference on VLSI Design (VLSID), August 1995, Page(s): 759-765.
    
    
49. D. Bhatia, R. Rajagopalan, and S. Katkoori, "Hierarchical Reconfiguration of VLSI/WSI Arrays," 7th International Conference on VLSI Design (VLSID), January 1994, Page(s): 349-352.