High Level Synthesis
Summary: High level synthesis is the process of generating a register level design from an algorithmic behavioral specification. The inputs to the system are the behavioral specification, a module library and the user constraints. The behavioral specification can be written in a high level general purpose language like C or in a Hardware Description Language like VHDL. The module library consists of storage units like registers and memories, execution units like adders and multipliers, and interconnect units like multiplexors and buses. Typical user constraints are area, clock speed and power. Traditionally, the output of the synthesis system consists of two interacting components namely data path and controller . The data path is built from the modules of the module library and the controller is a finite state machine to be implemented either as a PLA or a microprogram. High level synthesis is followed by logic and layout synthesis resulting in fabricatable mask layouts targeted for various technologies.
Research Problems:
Scheduling Algorithms
Register Optimization Techniques
Feedback between Physical Design and HLS
Summary: Excessive heat dissipation in modern microprocessors and limited power budget for high performance portable electronics have underlined the need for efficient low power design methodologies. The 1997 National Technology Road map for Semiconductors (NTRS), identifies excessive power consumption to be a serious limitation to the realization of future large systems on a chip. My doctoral dissertation at the University of Cincinnati was on the development of efficient high-level power estimation and power optimization algorithms for VLSI ASIC synthesis and were implemented in Profile Driven Synthesis System (PDSS). Currently, we are investigating into power optimization techniques at the system-level.
Research Problems:
Power Estimation at behavioral and
RT-levels
Power Optimization techniques
Summary: Rapidly shrinking feature sizes of both devices and interconnect in VLSI circuits to deep-sub micron (DSM) dimensions has resulted in a paradigm shift in the VLSI CAD problems. Physical phenomena (such as cross-talk, reflections, and IR drop on power lines) that were abstracted/ignored so far by the VLSI CAD tools become dominant. While devices are the key to the system performance in micron/sub-micron regime, interconnect is the key in the DSM regime. New CAD algorithms that effectively model, esimate, and optimize interconnect phenomena are acutely needed. Currently, the group is investigating in developing algorithms to model and optimize DSM effects at levels of design abstraction.
Research Problems:
High level modelling of DSM effects such as cross-talk
Power issues in DSM Regime
Switch-level Simulation
Optical interconnect for global interconnect
My research interests are focussed on the development Computer Aided Design (CAD) tools for automatic synthesis of Very Large Scale Integrated (VLSI) digital circuits and systems.
Excessive power consumption has been one of the major bottlenecks in today's high-performance ICs. With Suvodeep Gupta and Chandramouli Gopalakrishnan, I am investigating the development of power optimization techniques. Suvodeep is developing low-power scheduling algorithm(s) integrated into a high-level synthesis system known as AUDI system. Chandramouli is integrating leakage-power optimization techniques into AUDI system. AUDI stands for ``AUtomatic Design Instantiation'' and is recently developed by our research team. It is a behavioral synthesis system capable of automatically generating RT-level designs from high-level behavioral descriptions. AUDI system is currently the central vehicle in which we are incorporating majority of our synthesis solutions.
Today's capabilities to fabricate CMOS transistors at very small feature sizes (0.18 micron, as of today in production) has given rise to new challenges on the design automation front. The key paradigm shift in the deep-sub-micron (DSM) regime is the dominance of interconnect phenomena such as wire-delay, cross-talk, etc. The prestigious five-year CAREER award from the National Science Foundation is supporting our research addressing some of the synthesis challenges in the DSM regime. Specifically, we are developing an interconnect-centric behavioral synthesis system (AUDI), that unifies and/or establishes feedback with the low-level synthesis tasks/systems. With Stelian Alupoaei, I am also looking at developing new design methodology at Register transfer level of design abstraction.
Honeywell Inc., Clearwater, Florida has been supporting
our research on the problems related to Reconfigurable
Computing and Space Radiation hardened synthesis techniques.
Jeremy Ramos, Praveen Samudrala, Chandramouli Gopalakrishnan,
Suvodeep Gupta, and myself are looking at these problems.
In the past decade, FPGA-based systems have become popular
due to their versatility and low cost. With Dr. Wai-Kei Mak
and Hao Li, I am investigating into low-power FPGA synthesis
techniques.