1. P. Fernando and S. Katkoori, "An Elitist Non-Dominated Sorting based Genetic Algorithm for Simultaneous Area and Wirelength Minimization during VLSI Floorplanning," Submitted to IEEE Transactions on VLSI Systems. Under Review.

  2. V. Krishnan and S. Katkoori, "Stochastic Wirelength Estimation-based Iterative Binding for High Level Synthesis," IEEE Transactions on VLSI Systems. Under Review.

  3. H. Sankaran and S. Katkoori, "Simultaneous Scheduling, Allocation, Binding, Re-ordering, and Encoding for Crosstalk Pattern Minimization during High Level Synthesis," IEEE Transactions on VLSI Systems. To Appear, Accepted June 2009.

  4. P. Fernando and S. Katkoori, "A Customizable FPGA IP Core Implementation of a General Purpose Genetic Algorithm Engine," IEEE Transactions on Evolutionary Computation. To Appear, Accepted April 2009.

  5. V. Krishnan and S. Katkoori, "TABS: Temperature-Aware Layout Driven Behavioral Synthesis," IEEE Transactions on VLSI Systems. To Appear, Accepted March 2009.

  6. S. Roy, N. Ranganathan, and S. Katkoori, "A Framework For Power-Gating Functional Units in Embedded Microprocessors," IEEE Transactions on VLSI Systems, Accepted for publication, 2008.

  7. K. Vyas and S. Katkoori, ``A Genetic Algorithm for Design Space Exploration of Datapaths during High Level Synthesis," IEEE Transactions on Evolutionary Computation. Volume 10, Issue 3, June 2006 Page(s):213 - 229.

  8. S. Gupta and S. Katkoori, ``Intra Bus Crosstalk Estimation Using Word-Level Statistics," IEEE Transactions on Computer-Aided Design of ICs and Systems, Volume 24, Issue 3, March 2005, Page(s):469 - 478.

  9. P. K. Samudrala, J. Ramos, and S. Katkoori, ``Selective Triple Modular Redundancy (STMR) Based Single Event Upset (SEU) Tolerant Synthesis for FPGAs,'' IEEE Transactions on Nuclear Science, Volume: 51 , Issue: 5 , Oct. 2004, Pages:2957-2969.

  10. S. Alupoaei and S. Katkoori, ``Ant Colony System Application for Macrocell Overlap Removal," IEEE Transactions on VLSI Systems, Volume: 12 , Issue: 10 , Oct. 2004 Pages:1118 - 1123.

  11. S. Alupoaei and S. Katkoori, ``Net Clustering Based Constructive and Iterative Improvement Approaches for Macro-cell Placement,'' Journal on VLSI Signal Processing, Vol. 37, No. 1, May 2004, pp. 151-163.

  12. H. Li, S. Katkoori, and W. K. Mak, ``Power Minimization Algorithms for LUT Based FPGA Technology Mapping,'' ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 9, No. 1, January 2004, pp. 33-51.

  13. C. Gopalakrishnan, S. Katkoori, and S. Gupta, ``Power Optimization Using Input-based Transformations," Vol. 150, No. 3, May 2003, IEE Proceedings - Computers and Digital Techniques. pp. 133-142.

  14. S. Alupoaei and S. Katkoori, ``Net-Based Force-directed Macrocell Placement for Wirelength Optimization,'' IEEE Transactions on VLSI Systems, Vol. 10, No. 6, December 2002, pp. 824-835.

  15. R. Vemuri, S. Katkoori, M. Kaul, and J. Roy, ``An Efficient Hierarchical Register Optimization Algorithm for High Level Synthesis from Behavioral Specifications," ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 7, No. 1, January 2002, pp. 189-216.

  16. S. Katkoori and R. Vemuri, ``Architectural Power Estimation Based on Behavioral Profiling,'' Vol.7, No. 3, Journal on VLSI DESIGN , August, 1998, pp. 255-270.

  17. N. Kumar, S. Katkoori, L. Rader and R. Vemuri, ``Profile-Driven Behavioral Synthesis for Low Power VLSI Systems,'' IEEE Design & Test of Computers, Fall Issue, 1995, pp.70-84.

  1. H. Li, S. Katkoori, and W-K. Mak, "Force-Directed Performance Driven Placement Algorithm for FPGAs," Proceedings of International Symposium on VLSI 2004, pp. 193-198.

  2. C. Gopalakrishnan and S. Katkoori, ``Tabu Search Based Behavioral Synthesis of Low Leakage Datapaths,'' Proceedings of International Symposium on VLSI 2004, pp. 260-261.

  3. S. Gupta and S. Katkoori, ``A Fast Word-Level Estimation Technique for Intra-Bus Crosstalk,'' Proceedings of Design Automation and Test in Europe (DATE) Conference and Exhibition , 2004, Vol. 2, Feb. 16-20, pp. 1110-1115.

  4. S. Alupoaei and S. Katkoori, ``Energy Model Based Macrocell Placement for Wirelength Minimization,'' 17th International Conference on VLSI Design & 3rd International Conference on Embedded System, 2004, Jan. 5-9, Mumbai, pp. 713-716.

  5. S. Alupoaei and S. Katkoori, ``Ant Colony Optimization Technique for Macrocell Overlap Removal,'' 17th International Conference on VLSI Design & 3rd International Conference on Embedded System, 2004, Jan. 5-9, Mumbai, pp. 963-968.

  6. S. Gupta and S. Katkoori, ``Intra-Bus Crosstalk Estimation Using Word-Level Statistics,'' 17th International Conference on VLSI Design & 3rd International Conference on Embedded System, 2004, Jan. 5-9, Mumbai, pp. 449-454.

  7. C. Gopalakrishnan and S. Katkoori, ``KnapBind: An Area-Efficient Binding Algorithm for Low-leakage Datapaths,'' 2003 International Conference on Computer Design (ICCD), October 2003, pp. 430-435 .

  8. P. K. Samudrala, J. Ramos, and S. Katkoori, ``Selective Triple Modular Redundancy for SEU Mitigation in FPGAs,'' 2003 Military and Aerospace Applications of Programmable Logic and Devices (MAPLD) September 2003.
    Online Proceedings:
    http://klabs.org/richcontent/MAPLDCon03/abstracts/authors_2003.html

  9. C. Gopalakrishnan and S. Katkoori, ``A Fast Hierarchical Leakage Power Simulator for VHDL Structural Descriptions,'' International Symposium on VLSI (ISVLSI) 2003 , February 2003, pp. 211-212.

  10. H. Li, W. K. Mak, and S. Katkoori, ``An Efficient LUT-Based FPGA Technology Mapping Algorithm for Power Minimization,'' Asia-Pacific Design Automation Conference (ASPDAC), Japan, January 2003, pp: 353-358. (Nominated for Best Paper Award).

  11. C. Gopalakrishnan and S. Katkoori, ``Resource Allocation and Binding for Low Leakage Power,'' 16th International Conference on VLSI Design , January 2003, pp 297-302.

  12. C. Gopalakrishnan and S. Katkoori, ``Behavioral Synthesis of Datapaths with Low Leakage Power,'' IEEE International Symposium on Circuits and Systems (ISCAS), Volume: 4 , 2002 Page(s): 699 -702

  13. S. Gupta and S. Katkoori, ``Force-directed Scheduling for Dynamic Power Optimization,'' IEEE Computer Society Annual Symposium on VLSI (ISVLSI) , 2002, pp. 68-73.

  14. C. Gopalakrishnan and S. Katkoori, ``Power Optimization using Input Transformations," First International Workshop on Electronic Design, Test, & Applications (DELTA), January 29-31, 2002, pp. 154-158.

  15. S. Alupoaei and S. Katkoori, ``Net Clustering Based Macro-cell Placement,'' International Conference on VLSI Design , Bangalore, India, January 7-11, 2002, pp. 399-404.

  16. H. Li, W. K. Mak, S. Katkoori, ``Low Power Mapping for FPGAs with Optimal Depth,'' Proceedigns of IEEE Computer Society Workshop on VLSI , 19-20 April, Orlando, 2001, pages 123-128.

  17. S. Katkoori and S. Alupoaei, ``RT-level Interconnect Optimization in DSM Regime,'' Proceedings of IEEE Computer Society Workshop on VLSI , 27-28 April, Orlando, 2000, pages 143-148.

  18. S. Katkoori and R. Vemuri, ``Scheduling for Low Power under Resource and Latency Constraints,'' Proceedings of International Symposium on Circuits and Systems (ISCAS) 2000, Vol. 2, pages 53-56.

  19. A. Durbha and S. Katkoori, ``Route-and-Place Design Methodology for Interconnect Optimization in DSM Regime,'' Proceedings of the X IFIP International Conference on Very Large Scale Integration , Portugal, December 1999, pages 427-438.

  20. P. Maurer, S. Katkoori, W. Mak, M. Varanasi, ``Component-Level Programming: A Revolution in Software Technology,'' Proceedings of the Frontiers in Education Conference , Proceedings of the 29th Annual Frontiers in Education Conference, Vol. 2 , 1999, pages, 12B1/11 -12B1/15.

  21. S. Katkoori, N. Kumar, L. Rader and R. Vemuri, ``A Profile Driven Approach for Low Power Synthesis'', Proceedings of VLSI'95, Japan, August 29-September 1, pp. 759-765, 1995.

  22. S. Katkoori, N. Kumar and R. Vemuri, ``High Level Profiling Based Low Power Synthesis Technique'', Proceedings of International Conference on Computer Design 1995, Austin, October 2-5, pp. 759-765, 1995.

  23. S. Katkoori, and R. Vemuri, ``A Power Simulator for VHDL Structural Descriptions'', Proceedings of VIUF Fall Conference 1995, Boston, October 15-18, pp. 4.17-4.25, 1995.

  24. S. Katkoori, J. Roy, and R. Vemuri. ``A Hierarchical Register Optimization Algorithm for Behavioral Synthesis'', Proceedings of The 9th International Conference on VLSI Design, Bangalore, India, pp. 126-134, 1996.

  25. S. Katkoori and R. Vemuri, ``Simulation Based Architectural Power Estimation for PLA-Based Controllers", International Symposium on Low Power and Electronic Design 1996., 12-14 Aug. 1996 pp. 121 - 124.

  26. V. Natesan, A. Gupta, S. Katkoori, D. Bhatia, and R. Vemuri, ``A Constructive Method for Data Path Area Estimation During High-Level VLSI Synthesis'', Proceedings of Asia Pacific Design Automation Conference (ASPDAC), Chiba, Japan, 1997.

  27. R. Rajagopalan, S. Katkoori, and D. Bhatia, ``Hierarchical Reconfiguration of VLSI/WSI Arrays'', Proceedings of The 7th International Conference on VLSI Design, Calcutta, India, 1994.

Created and updated by Srinivas Katkoori
Last updated on Thu Aug 20 13:23:33 EDT 2009