Curriculum Vitae of


SRINIVAS KATKOORI
Associate Professor
Department of Computer Science and Engineering
University of South Florida

ADDRESS

• Office: 4202 East Fowler Avenue, ENB 118, Tampa, FL 33620.
  Email: katkoori@cse.usf.edu
  Phone: (813) 974-5737
  Fax: (813) 974-5456
  Webpage: http://vcapp.csee.usf.edu/~katkoori

RESEARCH INTERESTS

• High Level Synthesis
• Low Power Synthesis
• FPGA Based Synthesis
• Reconfigurable Computing
• Radiation Tolerant CAD for FPGAs
• Evolutionary Algorithms
• IC Reliability

EDUCATION

• Doctor of Philosophy, Computer Engineering1992-1998
  Department of ECECS, University of Cincinnati, Cincinnati.
  University Graduate Scholarship (UGS) for the entire duration of doctoral studies.
  1997-98 Outstanding Doctoral Dissertation, Honorable Mention, ECECS Dept.

• Bachelor of Engineering, Electronics and Communication Engineering 1988 - 1992
  Department of Electronics and Communication Engineering (ECE),
  Osmania University, Hyderabad, India.
  Admission by state wide Engineering entrance (EAMCET) test. Stood in top 1% of test takers.
  Passed in first class with distinction.

WORK EXPERIENCE

• Associate Professor Aug. 2004 - present
  Department of Computer Science and Engineering,
  University of South Florida, Tampa, Florida.

• Sabbatical Leave Aug. 2005 - Dec 2005
  Bio-Inspired Technologies & Systems
  NASA Jet Propulsion Labs (JPL), Pasadena, CA.

• Assistant Professor Aug. 1997 - July 2004
  Department of Computer Science and Engineering,
  University of South Florida, Tampa, Florida.

• Research Assistant 1993-95, 1996-97
  Digital Design Environments Laboratory (DDEL),
  Department of Electrical and Computer Engineering and Computer Science (ECE&CS),
  University of Cincinnati, Cincinnati, Ohio.

AWARDS & HONORS

• 2009 Certificate of Recognition by USF Computer Science & Engineering Department, ``For his leadership and outstanding service as Graduate Program Director,'' for service from May 2006 to April 2009.

• 2008 Elevation to Senior Member Status, Association of Computing Machinery (ACM).

• 2007 Certificate of Appreciation, Alfred P. Sloan Foundation, ``In appreciation for your commitment to advancing under-represented minority students in mathematics, science and engineering and for your leadership in the Alfred P. Sloan Foundation's Minority Ph.D. Program.''

• 2007-2008 USF Outstanding Undergraduate Teaching Award.

• Recognition of IEEECS student chapter with ``2003 Outstanding Chapter Award,'' under Dr. Katkoori's Advisorship.

• 2005 National-level IEEE-USA Professional Achievement Award. Nominated by IEEE Florida West Coast Section.

• 2005 Outstanding Engineering Educator Award, IEEE Florida Council Award (Region 3), Nominated by the IEEE Florida West Coast Section (FWCS).

• Member, Sigma Xi, The Scientific Research Society, 2004 (By Invitation).

• 2004 Elevation to Senior Member Status, IEEE.

• Best Paper Nomination at 2003 International Conference on Asian and South-Pacific Design Automation Conference (ASP-DAC).

• 2003 University of South Florida Outstanding Faculty Research Achievement Award.

• 2001 Faculty Early Career Development Grant (CAREER), National Science Foundation, Design Automation Program, to conduct research for five years on ``Interconnect centric High Level Synthesis in Deep-Sub-Micron Regime.''

• 1997-98 Outstanding Doctoral Dissertation, Honorable Mention, Department of Electrical and Computer Engineering and Computer Science, University of Cincinnati.

• Awarded sponsorship to attend NATO Advanced Study Institute Workshop entitled ``Low Power in Deep Submicron Electronics'', Italy, August 20-30, 1996.

• Research Assistantship, Digital Design Environments Laboratory, University of Cincinnati, June 1993-95, 1996-97

• University Graduate Scholarship, University Of Cincinnati, Fall 1992 - 1997

• Third Place at Under-Graduate level AP State Mathematics Olympiad, India, 1990.

RESEARCH GRANTS & CONTRACTS

• National Science Foundation, CCF 2010 - 2011
  Title: CADathlon 2010: International Graduate
  Student Progg. Contest in EDA
  Amount: $10,000
  Status: PI. Co-PIs: S. Pasricha (CSU), J. Roy, and S. Banerjee.

• National Science Foundation, 2006 - 2008
  Title: CRI: Infrastructure acquisition for
  sub-100 nano VLSI research
  Amount: $215,023
  Role: Co-PI. PI: S. Bhanja (EE), Co-PIs: H. Zheng, N. Ranganathan, and V.K. Jain (EE).

• NASA Jet Propulsion Labs (JPL) RHESE Project2006
  Title: Hardware and Software Implementations of Intelligent and Evolvable Algorithms
  Amount: $100,000
  Role: Sole PI. Sub-contract to USF by NASA JPL.

• I4 High Tech Corridor Initiative 2003-2004
  (Industry Partner: Honeywell, Inc, Clearwater)
  Title: STMR based Software Tool and Application
  Development Targeted to HRSC Board
  Amount: $45,000
  Role: Sole PI.

• I4 High Tech Corridor Initiative 2002-2003
  (Industry Partner: Honeywell, Inc, Clearwater)
  Title: Requirements Analysis for an Automatic Synthesis
  Framework for Honeywell Reconfigurable Space Computer
  Amount: $25,000
  Role: Sole PI.

• National Science Foundation, Design Automation Program2001 - 2005
  Faculty Early Career Development Grant (CAREER)
  Title: CAREER: Interconnect-centric High-Level Synthesis
  in Deep Sub-Micron (DSM) Regime
  Amount: $310,000
  Role: Sole PI.

• I4 High Tech Corridor Initiative 2000-2001
  (Industry Partner: Honeywell, Inc, Clearwater)
  Title: High-Throughput and Low-Power Implementations of
  Space-Based Radar Algorithms on RC Hardware
  Amount: $150,000
  Role: Sole PI.

• Honeywell Incorporation 2001-2002
  SASSO/CSO Academic Initiatives IR&D Program 2001
  Title: SEU-tolerant Synthesis for FPGA based Space Systems
  Amount: $11,000
  Role: Sole PI.

• Honeywell Space Systems Inc. 2000-2001
  SASSO/CSO Academic Initiatives IR&D Program 2000
  Title: Reconfigurable Computing Architectures for Payload Processing
  (Signal & Datastream) Applications
  Amount: $13,000
  Role: Sole PI.

• Design Automation Graduate Scholarship 1999 - 2000
  Design Automation Conference Council
  Title: RT-level Route-and-Place Design Methodology
  for Delay and Power Optimization in DSM Regime
  Amount: $24,000
  Proposed for Stelian Alupoaei and Udaykumar Anumalachetty

• Research & Creative Scholarship, 1997 - 98
  University of South Florida Research Council and
  Division of Sponsored Programs.
  Title: Interconnect Power Analysis and Optimization
  in High Level Synthesis Framework
  Amount: $7,500.00

PROFESSIONAL MEMBERSHIPS

• Association for Computing Machinery (ACM)
• ACM Special Interest Group on Design Automation (SIGDA)
• The Institute of Electrical and Electronics Engineers (IEEE)
• IEEE Computer Society
• IEEE Circuits and Systems Society
• Sigma Xi, The Scientific Research Society

TEACHING EXPERIENCE

• Associate Professor, Department of Computer Science & Engineering, University of South Florida, August 2004 -present.

• Assistant Professor, Department of Computer Science & Engineering, University of South Florida, August 1997 - July 2004.

• Teaching Assistant, Department of ECE&CS, University of Cincinnati, 1995-1996.

• Completed ``Advanced Teaching Techniques,'' course offered bi-annually by the Department of Advanced Teaching Institute, University of Cincinnati, Winter 1994.

• Attended a Teaching Workshop entitled ``Preparing Future Faculty,'' Division of Research and Advanced Studies, University of Cincinnati, May 1996.

LIST OF ALL COURSES TAUGHT AT USF

Undergraduate Courses

• Computer Organization (Gate Course)
• Computer Logic Design (Core Course)
• Computer Architecture (Core Course)
• Computer System Design (Core Course)
• CMOS VLSI Design (Core Course)
• Digital Circuit Synthesis (Senior Elective)
• CMOS VLSI Testing (Senior Elective)
• Advanced Computer Architecture (Senior Elective)

Graduate Courses

• Principles of Computer Architecture (Core Course)
• CMOS VLSI Design
• Low Power CMOS VLSI Design
• Digital Circuit Synthesis
• Testing & Fault Tolerance in Digital Systems

COURSE OFFERINGS (SEMESTER-BY-SEMESTER)

Undergraduate Core Courses:

• Computer Organization (CDA 3103)
  Offered in: Fall 2009.

• Computer Logic Design (EEL 4705 / CDA 3201)
  Offered in: Fall 1999, Fall 2000. Note: Course number changed in Fall 2000.

• Computer Organization & Architecture (CDA 4100)
  Offered in: Summer 1998, Spring 1998, Spring 1999, Summer 2000, Fall 2002, Fall 2003.

• Computer System Design (CDA 4203) & Lab (CDA 4203L)
  Offered in: Fall 1997, Fall 2007.

• CMOS VLSI Design (CIS 4213) & Lab (CDA 4213L)
  Offered in: Spring 2004, Spring 2005, Fall 2006, Fall 2008, Fall 2009.

Undergraduate Senior Electives:

• Advanced Computer Architecture
  Offered in: Spring 2000.

• Digital Circuit Synthesis
  Offered in: Spring 2002, Spring 2003, Fall 2004, Spring 2008.

• CMOS VLSI Testing
  Offered in: Spring 2007.

Graduate Core Courses:

• Principles of Computer Architecture (EEL 6764 001)
  Offered in: Fall 1998, Spring 1998, Fall 1999, Spring 2000.

Graduate Electives:

• CMOS VLSI Design
  Offered in: Spring 2000, Fall 2000, Fall 2001, Spring 2003, Spring 2004, Spring 2005, Fall 2006, Fall 2009, Spring 2009.

• Low Power CMOS VLSI Design and CAD
  Offered in: Fall 1998, Spring 2000, Spring 2001, Spring 2002.

• Advanced Computer Architecture
  Offered in: Spring 2000.

• Digital Circuit Synthesis
  Offered in: Spring 2002, Fall 2003, Fall 2004, Fall 2005, Spring 2008.

• Testing & Fault Tolerance in Digital Systems (EEL 6706 001)
  Offered in: Spring 2007.

NEW COMPUTER ENGINEERING COURSES DEVELOPED AT USF

• Digital Circuit Synthesis: This course is a dual-level course (advanced Senior Elective as well as Graduate Elective) for Computer Engineering students. The main learning outcomes are: (a) familiarity with principles of high-level electronic design automation (EDA) of digital circuits; (b) development of behavioral and structural VHDL models; (c) experience in using the state-of-the-art industry-strength VHDL simulator; and (d) experience in coding synthesis algorithms in C/C++. The main focus is on high-level (behavioral) synthesis and logic synthesis algorithms. VHDL, a hardware description language widely used in EDA industry, is introduced in this course. Students develop behavioral and gate-level library in VHDL and validate it using CADENCE VHDL simulator. For the final project, students code a basic data-path synthesis tool in C/C++ that accepts a data flow graph and the VHDL component library and generates a valid RT-level datapath and associated controller in VHDL. Parallels between software compilation and silicon compilation are drawn. Two texts are used, namely, ``Synthesis and Optimization of Digital Circuits,'' by Giovanni De Micheli, and ``The Student's Guide to VHDL,'' by Peter Ashenden.

• Low Power CMOS VLSI Design: This course is an advanced graduate elective that introduces students to the estimation and optimization techniques of power consumption in CMOS VLSI designs at all levels of design abstractions (physical, logic, RT-level, behavioral, and system). Over last two decades, power optimization has emerged as an important design objective, besides the traditional area and timing objectives. As power optimization is a highly active research area, the students learn about latest power estimation and optimization techniques by reviewing survey papers as well as latest research papers published in conferences and archival journals. As a final project, the students can choose between the following: (a) Software project: need to implement a published power estimation algorithm in C/C++; or (b) Hardware project: need to implement a published power optimization technique (such as Guarded Evaluation or Pre-computation) at gate-level or layout-level. The course text is a collection of papers from the literature.

ENHANCING COMPUTER ENGINEERING COURSE CURRICULUM AT USF

• CMOS VLSI Design and Lab (CDA 4213/CIS 6930): This is a dual level course. For Computer Engineering undergraduates, this course is a core course. For Graduate students, this is an introductory course and is a pre-requisite for other graduate courses such as Digital Circuit Synthesis, Low Power VLSI Design, VLSI Testing, etc. Topics include, CMOS technology, MOSFET operation, non-ideal behavior of MOSFETs, bit-sliced (modular) design, delay and power models, PLAs and memory (SRAM and DRAM), interconnect, reliability, etc.

  Course Enhancements: In the current deep-sub-micron regime, several new design factors have emerged as key determinants of system performance. The lecture is enhanced to cover these topics in more depth: (a) interconnect design and analysis; (b) detailed delay estimation and optimization based on logical effort; and (c) power estimation and optimization techniques.

  Dr. Katkoori introduced a co-requisite design lab in which students learn and use CADENCE Virtuoso (Layout editor) for circuit layout and extraction followed by detailed simulation with Synopsys HSPICE and nanosim. As part of weekly assignments, basic cell library is built which is used in the final project. Students in groups of two (graduates) or three (undergraduates) design a digital thermometer ASIC that can log average, minimum, and maximum temperatures and can report in either Celsius or Fahrenheit scales. The main design constraint is on the chip area of approximately 1 mm x 1mm. The layout is integrated with the MOSIS pad frame (Tiny Chip) and is fabricated via MOSIS Educational Program. The fabricated ICs are tested in the following semester either in CMOS VLSI Testing course or as an independent study (if the testing course is not offered). The textbook for the course is ``CMOS VLSI Design - A Circuits and Systems Perspective,'' by Neil Weste and David Harris.

• Computer System Design & Lab (CDA 4203): From Fall 2008, this is an advanced core course for Computer Engineering undergraduate majors and a recommended elective to Computer Science majors. Prior to CDA 4203, the students have dealt the hardware design and software development as two different and independent activities. In this course, for the first time, the student will see the interplay between hardware design and associated software development.

  Course Enhancements: In 2006 ABET Mock visit, the Computer Engineering Program Evaluator (Dr. Joe Hughes, Georgia Tech) in the Final Report has indicated that the Computer System Design and associated Lab needs a major overhaul for successful ABET Accreditation of the program. The following is the relevant excerpt from the Mock Visit Final report: ``The computer engineering curriculum appears to be satisfactory, with the exception of system design related to hardware/software interactions and trade-offs. There appears to be a broadly perceived need to revisit the existing hardware-oriented course sequence (both required and electives) to eliminate redundancy and provide more content and hands-on experience in hardware/software systems and co-design."

  In response to the above, Dr. Katkoori in consultation with senior hardware faculty (Dr. N. Ranganathan) has taken lead: (a) to re-design the course lecture as well as (b) architect and implement a brand new companion lab (CDA 4203L).

  • The lecture is enhanced in the following ways: (a) highly interactive class room discussions; (b) mini-projects that require independent research on COTS components and system design; (c) digital camera design project; (d) structured system design approach; (e) analysis of hardware/software trade-offs; and (f) a new text is adapted, namely, Embedded System Design - A Unified Hardware/Software Introduction, by Frank Vahid and Tony Givargis.

  • The design lab is enhanced as follows: (a) Xilinx University Program Virtex II Pro (XUP V2P) board is used as a design platform. The board consists of Virtex II Pro FPGA, two embedded PowerPC processors, memory, transceivers, Clock Managers, and variety of I/O interfaces (Ethernet, Serial, parallel, USB interface, Audio/Video, and PS/2). Using this board, the student can gain great experience in hardware and software interfacing; (b) 10 design work stations, each equipped with a PC, XUP V2P FPGA board, logic analyzer, PC-based oscilloscope, bread-board, etc., are developed. These workstations are also used in CMOS VLSI Testing and FPGA design courses.

  In Fall 2008, the Computer Engineering program has been successfully accredited for another 6 years.

• Testing & Fault Tolerance of Digital Systems (CIS 4930/EEL 6706): This course was regularly taught by another Computer Engineering faculty member. After he had left USF, this course was dormant for 5+ years. Dr. Katkoori has taken initiative to teach this course, as it will enhance a Computer Engineering student's repertoire and improves their chances of employment with leading IC design companies. Topics include fault models (single- and multiple- stuck-at-fault models), detectable and undetectable faults, fault simulation, test generation algorithms (Critical Path Tracing, D-algorithm), memory testing, design-for-testability, built-in-self-test, and contemporary testing topics. As part of the course assignments, students code an ATPG algorithm. The ICs fabricated in CMOS VLSI class are used for testing experience with logic analyzers. The course textbook is ``Digital Systems Testing and Testable Design,'' by M. Abramovici, M. A. Breuer, and A. D. Friedman.

VLSI CAD TOOL RELATED EXPERTIZE

• Physical Design: CADENCE Tool Suite (Virtuoso), MAGIC, HSPICE, Nanosim, Fire & Ice, Celtic Crosstalk Analyzer.
• Logic Synthesis: SIS, Synopsys Tool Suite
• High-level Synthesis: Developed AUDI (Automatic Design Instantiation), an in-house high-level synthesis system in C language. This system is extended by several PhD and MS students for their thesis work.
• FPGA Related Tools: Xilinx ISE, Embedded Design Kit (EDK).
• Hardware Description Languages (HDLs): VHDL and Verilog.
• Automatic Translators/Parsers: lex, flex, yacc, bison, ANTLR.
• Other Languages: C, C++, Java, Unix shell scripting, Awk, sed.

GRADUATE STUDENT SUPERVISION

• PhD Theses supervised
  1. Dr. Soumyaroop Roy (PhD Candidate) Summer 2005 - Summer 2010
     Co-advised with Dr. N. Ranganathan, CSE, USF)
     Dissertation Title: Architecture and Compiler Support for Leakage Reduction Using Power Gating in Microprocessors
     First Employment: AMD, Texas, Austin.

  2. Dr. Pradeep Fernando Summer 2005 - Fall 2009
     Dissertation Title: Genetic Algorithm Based Design and Optimization of VLSI ASICs and Reconfigurable Hardware
     First Employment: Post-doc, EPFL, Lausanne, Switzerland.

  3. Dr. Hariharan Sankaran Spring 2003 - Fall 2008
     Dissertation Title: High-Level Synthesis Framework for Crosstalk Minimization in VLSI ASICs
     First Employment: Synopys, Bangalore, India.

  4. Dr. Vyas Krishnan Spring 2003 - Fall 2008
     Dissertation Title: Temperature And Interconnect Aware Unified Physical And High Level Synthesis
     First Employment: Assistant Professor, St. Leo University, Tampa, FL.

  5. Dr. Suvodeep Gupta Spring 2002 - Fall 2004
     Dissertation Title: Behavioral and RT-level Cross-talk Estimation and Optimization in VLSI ASICs
     First Employment: Intel, Phoenix, AZ.

  6. Dr. Hao Li (Co-advised with Dr. W-K. Mak)Fall 1999 - Fall 2004
     Dissertation Title: Low Power Technology Mapping and Performance Driven Placement for Field Programmable Gate-Arrays
     First Employment: Assistant Professor, CSE, University of North Texas at Denton.
     Currently working for Synopsys Inc, San Jose, CA.

  7. Dr. Chandramouli Gopalakrishnan Spring 2000 - Fall 2003
     Dissertation Title: High Level Techniques for Estimation and Optimization of Leakage Power of VLSI ASICs
     First Employment: CADENCE, Noida India.
     Currently working for Synopsys Inc, Bangalore, India.

  8. Dr. Stelian Alupoaei Summer 1999 - Spring 2003
     Dissertation Title: Interconnect-centric Macrocell Placement Approaches in DSM Regime
     First Employment: Intel, Portland, OR.

• PhD Theses currently supervising
  1. Shilpa Pendyala, PhD Candidate Fall 2009 - present
     Topic: High level Synthesis
     Master's in Computer Science from Univ. of Missouri Rolla.
     

• MS Theses supervised
  1. Ananth Durbha Summer 1998 - Fall 1999
     Thesis Title: A Novel Route-and-Place RTL Design Methodology for Interconnect Optimization in DSM Regime.
     First Employment: Intel Corporation, Santa Clara, CA.

  2. Smitha Myneni Fall 1997 - Spring 2000
     Thesis Title: Development of Accurate Power Simulator using hierarchical VHDL Specification.
     First Employment: Intel Corporation, Santa Clara, California.

  3. Chandramouli Gopalakrishnan Fall 1997 - Fall 2000
     Thesis Title: Power Optimization via Input Transformations.
     Continued for a doctoral degree.

  4. Gayatri Garudadri
     Project Title: Register Transfer (RT) Level Simulation of the MIPS Pipelined Processor in JAVA.
     First Employment: Software Company, Tampa, Florida.

  5. Suvodeep Gupta Fall 1999 - Spring 2002
     Thesis Title: Force-directed Scheduling for Dynamic Power Optimization.
     Continued for a doctoral degree.

  6. Joe Rogers (Co-advised with Dr. Ken Christensen) Fall 1998- Summer 2002
     Thesis Title: Network Traffic Study of Internet2.
     First Employment: Academic Computing, USF.

  7. Praveen Samudrala Fall 2001 - Spring 2003
     Thesis Title: Selective Triple Modular Redundancy based Single Event Upset (SEU) Mitigation for FPGAs
     First Employment: SpaceMicro Corporation, San Diego.
     Currently working for Qualcomm, San Diego.

  8. Praveen Bamini Fall 2001 - Fall 2003
     Thesis Title: Implementation of a Speech Synthesis System.
     First Employment: Verizon, Tampa, FL.

  9. Anulekha Bilhanan Fall 2001 - Spring 2004
     (Co-advised with Dr. John Heine, Moffitt Cancer Research Institute)
     Thesis Title: Implementation of Mammograph analysis algorithms on FPGA.
     First Employment: Fischer Imaging Inc, Denver, CO.

  10. Umadevi Kailasam Fall 2001 - Spring 2004
      Thesis Title: High Level VHDL Modeling of a Low-Power ASIC for a Tour Guide.
      First Employment: Golden Gate Technology, San Jose, CA.

  11. Viswanath Daita Fall 2002 - Fall 2004
      (Co-advised with Dr. Wilfredo Moreno, EE, USF)
      Thesis Title: Behavioral VHDL Implementation of Coherent Digital GPS Signal Receiver.

  12. Ranganath Gopalan Fall 2002 - Spring 2005
      Thesis Title: Behavioral Synthesis of Low Leakage Pipelined Datapaths
      First Employment: Intel, San Jose, CA.

  13. Hariharan Sankaran Fall 2001 - Summer 2005
      Thesis Title: System level energy optimization for location aware computing.
      Continued for a doctoral degree.

  14. Sujana Kakarla Fall 2003 - Spring 2005
      Thesis Title: Partial Evaluation Based Triple Modular Redundancy for SEU Mitigation.

  15. Supriya Sunki Fall 2003 - Summer 2005
      Thesis Title: Performance optimization in three-dimensional programmable logic arrays (PLAs).

  16. Pradeep Fernando Fall 2003 - Summer 2005
      Thesis Title: Genetic Algorithm Based Two-Dimensional and Three-Dimensional Floorplanning for VLSI ASICs
      Continued for a doctoral degree.

  17. Soumyaroop Roy Fall 2003 - Summer 2005
      (Co-advised with Dr. N. Ranganathan, CSE, USF)
      Thesis Title: A Compiler Based Leakage Reduction Technique by Power-Gating Functional Units in Embedded Microprocessors
      Continued for a doctoral degree.

  18. Nagalakshmi Subramanya Spring 2007 - Summer 2008
      (Co-advised student with Dr. R. Tripathi, CSE, USF)
      Thesis Title: Study of FPGA implementation of entropy norm computation for IP data streams

  19. Mark La Spina Spring 2009 - Spring 2010
      Thesis Title: Parallel Genetic Algorithm Engine on an FPGA
      

• MS Theses currently supervising
  1. Chris Bell Fall 2011 - current
     Topic: Secure Hardware Design

  2. Matthew Lewandowski Fall 2011 - current
     Topic: Secure Hardware Design

  3. Richard Meana Fall 2011 - current
     Topic: Secure Hardware Design

• UNDERGRADUATE SUPERVISION
  • Daniel Ashley, REU Project, Fall 2011.
  • Richard Meana, Senior Project, Fall 2011.
  • Matthew Lewandowski, Senior Project, Fall 2011.
  • Chris Bell, REU Project, Spring 2011.
  • Matthew Lewandowski, REU Project, Spring 2011.
  • Richard Meana, REU Project, Spring 2011.
  • Qi Zhao, Senior Project, Fall 2009.
  • Khris Martinez, Senior Project, Fall 2009.
  • Rey Cablong, Senior Project, Fall 2009.
  • Andrew Mast, Senior Project Spring 2008.
  • Jamie Montelegre, Senior Project, Spring 2008.
  • Luke Jenkins, Senior Project, Spring 2008.
  • Bhavna Kumar, REU, Spring 2005.
  • Ryan Mabry, REU, Summer 2004.
  • Billy Klerk, REU, Summer 2004.
  • Andrew White, Senior Project, Spring 2003.
  • Jeremy Ramos, Senior Project & McNairs Scholar, Fall 2000.

PATENTS

1. Method and apparatus for creating circuit redundancy in programmable logic devices, Praveen K. Samudrala, Srinivas Katkoori, and Jeremy Ramos. US Patent No. 6,963,217.

   Abstract: A method for reducing circuit sensitivity to single event upsets in programmable logic devices, involves identifying single event upset sensitive gates within a single event upset sensitive sub-circuit of a programmable logic device as determined by the input environment and introducing triple modular redundancy and voter circuits for each single event upset sensitive sub-circuit so identified.

INVITED TALKS

• Drexel University, Philadelphia, PA.
• Arizona State University, Tempe, AZ.
• University of Tennessee, Knoxville, TN.
• Rochester Institute of Technology, Buffalo, NY.
• University of Texas, El Paso, TX.
• Honeywell Space Systems, Clearwater, FL.
• Osmania University, Hyderabad, India.
• Navigational Electronics Research & Training Unit (NERTU), Osmania University, Hyderabad, India.
• National Institute of Technology (NIT, formerly REC), Warangal, India.
• AFRL Workshop on Radiation Hardening by Design, Albuquerque, NM.
• University of Southern California, CA.
• Jet Propulsion Laboratory, CalTech, Pasadena, CA.
• IBM, Seminar on Selective Triple Modular Redundancy.
• Center for Ocean Technology, College of Marine Science, USF.
• University of North Texas, Denton.
• Georgia Institute of Technology, Atlanta.
• Univ. of Southern California, LA.
• Seminar Speaker, Center for Communication & Signal Processing (CCSP), USF.
• Communications Network Group, USF.

BOOKS

1. V. Krishnan and S. Katkoori, ``Algorithms for Interconnect and Temperature Aware Unified Physical and High Level Synthesis, '' Springer Publishers, Manuscript In Preparation.

LIST OF PUBLICATIONS

Peer-Reviewed Journal Articles

1. H. Sankaran and S. Katkoori, ``Simultaneous Scheduling, Allocation, Binding, Re-ordering, and Encoding for Crosstalk Pattern Minimization during High Level Synthesis,'' IEEE Transactions on VLSI Systems, Volume 19, Issue 2, Feb. 2011, Page(s): 217 - 226.

2. S. Roy, N. Ranganathan, and S. Katkoori, ``State-Retentive Power Gating of Register Files in Multicore Processors Featuring Multithreaded In-Order Cores,'' IEEE Transactions on Computers, Volume 60, Issue 11, Nov. 2011 Page(s): 1547 - 1560

3. V. Krishnan and S. Katkoori, ``TABS: Temperature-Aware Layout Driven Behavioral Synthesis,'' IEEE Transactions on VLSI Systems, Volume 18, Issue 12, 2010, Page(s): 1649 - 1659

4. P. Fernando and S. Katkoori, D. Keymeulen, R. Zebulum, and A. Stoica, ``A Customizable FPGA IP Core Implementation of a General Purpose Genetic Algorithm Engine,'' IEEE Transactions on Evolutionary Computation, Volume 14, Issue 1, 2010, Page(s):133 - 149.

5. S. Roy, N. Ranganathan, and S. Katkoori, ``A Framework For Power-Gating Functional Units in Embedded Microprocessors,'' IEEE Transactions on VLSI Systems, Volume 17, Issue 11, Nov. 2009 Page(s):1640 - 1649.

6. K. Vyas and S. Katkoori, ``A Genetic Algorithm for Design Space Exploration of Datapaths during High Level Synthesis,'' IEEE Transactions on Evolutionary Computation, Volume 10, Issue 3, June 2006 Page(s):213 - 229.

7. S. Gupta and S. Katkoori, ``Intra Bus Crosstalk Estimation Using Word-Level Statistics," IEEE Transactions on Computer-Aided Design of ICs and Systems, Volume 24, Issue 3, March 2005 Page(s):469 - 478.

8. P. K. Samudrala, J. Ramos, and S. Katkoori, ``Selective Triple Modular Redundancy (STMR) Based Single Event Upset (SEU) Tolerant Synthesis for FPGAs,'' IEEE Transactions on Nuclear Science, Volume: 51 , Issue: 5 , Oct. 2004, Pages: 2957-2969.

9. S. Alupoaei and S. Katkoori, ``Ant Colony System Application for Macrocell Overlap Removal,'' IEEE Transactions on VLSI Systems, Volume: 12 , Issue: 10 , Oct. 2004 Pages:1118 - 1123.

10. S. Alupoaei and S. Katkoori, ``Net Clustering Based Constructive and Iterative Improvement Approaches for Macro-cell Placement,'' Journal on VLSI Signal Processing, Vol. 37, No. 1, May 2004, pp. 151-163.

11. H. Li, W. K. Mak, and S. Katkoori, ``Power Minimization Algorithms for LUT Based FPGA Technology Mapping,'' ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 9, No. 1, January 2004, pp. 33-51.

12. C. Gopalakrishnan, S. Katkoori, and S. Gupta, ``Power Optimization Using Input-based Transformations,'' Vol. 150, No. 3, May 2003, IEE Proceedings - Computers and Digital Techniques, pp. 133-142.

13. S. Alupoaei and S. Katkoori, ``Net-Based Force-directed Macrocell Placement for Wirelength Optimization,'' IEEE Transactions on VLSI Systems, Vol. 10, No. 6, December 2002, pp. 824-835.

14. R. Vemuri, S. Katkoori, M. Kaul, and J. Roy, ``An Efficient Hierarchical Register Optimization Algorithm for High Level Synthesis from Behavioral Specifications,'' ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 7, No. 1, January 2002.

15. S. Katkoori and R. Vemuri, ``Architectural Power Estimation Based on Behavioral Level Profiling,'' pp. 255-270, Vol.7, No. 3, Journal on VLSI Design, 1998.

16. N. Kumar, S. Katkoori, L. Rader and R. Vemuri, ``Profile-Driven Behavioral Synthesis for Low Power VLSI Systems,'' IEEE Design & Test of Computers, Fall Issue, pp.70-84, 1995.

Journal Articles - Under Review

1. P. Fernando and S. Katkoori, ``An Elitist Non-Dominated Sorting based Genetic Algorithm for Simultaneous Area and Wirelength Minimization during VLSI Floorplanning,'' IEEE Transactions on VLSI Systems, Submitted July 2009. Status: Revise and Resubmit (October 2009)

2. S. Roy, N. Ranganathan, and S. Katkoori,``Impact of Compiler Optimization Techniques on Power Gating for Leakage Reduction A Framework For Power-Gating Functional Units in Embedded Microprocessors,'' IEEE Transactions on Computers, Submitted August 2009.

Refereed Conferences

1. S. Roy, N. Ranganathan, and S. Katkoori, "Compiler Directed Power Gating in Embedded Microprocessors," IEEE International Conference on Computer Design (ICCD), October 2009, Page(s): 35-40.

2. S. Roy, N. Ranganathan, and S.Katkoori, "Exploration of Compiler Optimization Techniques for Enhancing Power Gating," IEEE International Symposium on Circuits and Systems (ISCAS), May 2009, Page(s): 1004-1007.

3. H. Sankaran and S. Katkoori, ``Floorplan Driven High Level Synthesis for Crosstalk Noise Minimization in Macro-cell Based Designs,'' IEEECS Annual Symposium on VLSI (ISVLSI), May 2009, Page(s): 274 - 279.

4. H. Sankaran and S. Katkoori, ``On-chip Dynamic Worst-case Crosstalk Pattern Detection and Elimination for Bus-based Macro-cell Designs,'' International Symposium on Quality Electronic Design (ISQED), March 2009, Page(s): 33 - 39.

5. V. Krishnan and S. Katkoori, ``Simultaneous Peak Temperature and Average Power Minimization during Behavioral Synthesis,'' 22nd International Conference on VLSI Design (VLSID), January 2009, Page(s): 419 - 424.

6. H. Sankaran and S. Katkoori, ``Simultaneous Scheduling, Allocation, Binding, Re-ordering, and Encoding for Crosstalk Pattern Minimization during High Level Synthesis,'' IEEE Computer Society Annual Symposium on VLSI (ISVLSI), April 2008, Page(s): 423 - 428.

7. H. Sankaran and S. Katkoori, ``Bus Binding, Re-ordering, and Encoding for Crosstalk-producing Switching Activity Minimization during High Level Synthesis,'' 4th IEEE Symposium on Electronic Design, Test, and Applications (DELTA), January 2008, Page(s): 454 - 457.

8. P. Fernando, H. Sankaran, S. Katkoori, D. Keymeulen, A. Stoica, R. Zebulum, R. Ramesham ``A Customizable FPGA IP Core Implementation of a General-Purpose Genetic Algorithm Engine,'' IEEE International Symposium on Parallel and Distributed Processing (IPDPS) 2008, April 2008, Page(s): 1 - 8.

9. V. Krishnan and S. Katkoori, ``A 3D-Layout Aware Binding Algorithm for High-Level Synthesis of Three-Dimensional Integrated Circuits,'' 8th International Symposium on Quality Electronic Design (ISQED), March 2007, Page(s): 885-892.

10. V. Krishnan and S. Katkoori, ``Minimizing wire delays by net-topology aware binding during floorplan- driven high level synthesis,'' 2007 IFIP International Conference on Very Large Scale Integration (VLSI-SOC), October 2007, Page(s):99-104.

11. P. Fernando and S. Katkoori, ``An Elitist Non-Dominated Sorting Based Genetic Algorithm for Simultaneous Area and Wirelength Minimization in VLSI Floorplanning,'' 21st International Conference on VLSI Design (VLSID), January 2008, Page(s): 337 - 342.

12. V. Krishnan and S. Katkoori ``Clock Period Minimization with Iterative Binding Based on Stochastic Wirelength Estimation during High-Level Synthesis,'' 21st International Conference on VLSI Design (VLSID), January 2008, Page(s): 641 - 646.

13. A. Stoica, R. Zebulum, D. Keymeulen, R. Ramesham, J. Neff, and S. Katkoori, ``Temperature-Adaptive Circuits on Reconfigurable Analog Arrays,'' IEEE Aerospace Conference, March 2007, Page(s): 1 - 6. (No hardcopy proceedings.)

14. D. Keymeulen, R. Zebulum, R. Rajeshuni, A. Stoica, S. Katkoori, S. Graves, F. Novak, and C. Antill, ``Extreme Temperature Electronics based on Self-Adaptive System using Field Programmable Gate Array,'' IEEE Aerospace Conference, March 2007, Page(s):1 - 6. (No hardcopy proceedings.)

15. W. Alvis, W.; S. Murthy, K. Valavanis, W. Moreno, M. Fields, and S. Katkoori, ``FPGA based flexible autopilot platform for unmanned systems,'' 2007 Mediterranean Conference on Control & Automation (MED), June, 2007, Page(s): 1 - 9.

16. S. Roy, S. Katkoori, and N. Ranganathan, ``A Compiler Based Leakage Reduction Technique by Power-Gating Functional Units in Embedded Microprocessors,'' 20th International Conference on VLSI Design (VLSID), January 2007, Page(s): 215-220.

17. D. Keymeulen, R. Zebulum, R. Rajeshuni, A. Stoica, S. Katkoori, S. Graves, F. Novak, and C. Antill, ``Self-Adaptive System Based on Field Programmable Gate Array for Extreme Temperature Electronics,'' First NASA/ESA Conference on Adaptive Hardware and Systems (AHS), June 2006 Page(s):296 - 300.

18. A. Stoica, R. S. Zebulum, D. Keymeulen, R. Ramesham, J. Neff, and S. Katkoori, ``Temperature-Adaptive Circuits on Reconfigurable Analog Arrays,'' First NASA/ESA Conference on Adaptive Hardware and Systems (AHS), June 2006 Page(s):28 - 31.

19. V. Krishnan and S. Katkoori, ``Design Space Exploration of RTL Datapaths using Rent Parameter based Stochastic Wirelength Estimation,'' 7th International Symposium on Quality Electronic Design (ISQED), March 2006, Page(s): 363 - 369.

20. R. Gopalan, C. Gopalakrishnan, and S. Katkoori, ``Leakage Power Driven Behavioral Synthesis of Pipelined Datapaths,'' IEEE Computer Society Annual Symposium on VLSI (ISVLSI), May 2005, Page(s):167 - 172.

21. H. Sankaran, S. Katkoori, and U. Kailasam, ``System Level Energy Optimization for Location-Aware Computing,'' IEEE Conference on Pervasive Computing (PerCom), March 2005, Page(s):319 - 323.

22. H. Li, S. Katkoori, and Z. Liu, ``Feedback Driven High Level Synthesis for Performance Optimization,'' 6th International Conference On ASIC (ASICON), Volume 2, October 2005, Page(s): 961 - 964.

23. H. Li, S. Katkoori, and W-K. Mak, ``Force-Directed Performance Driven Placement Algorithm for FPGAs,'' Proceedings of IEEE Computer society Annual Symposium on VLSI (ISVLSI), February 2004, Page(s):193 - 198.

24. C. Gopalakrishnan and S. Katkoori, ``Tabu Search Based Behavioral Synthesis of Low Leakage Datapaths,'' IEEE Computer society Annual Symposium on VLSI (ISVLSI), February 2004, Page(s): 260 - 261.

25. S. Gupta and S. Katkoori, ``A Fast Word-Level Estimation Technique for Intra-Crosstalk,'' Design, Automation and Test in Europe (DATE) Conference, Volume 2, February 2004, Page(s): 1110-1115.

26. S. Alupoaei and S. Katkoori, ``Energy Model Based Macrocell Placement for Wirelength Minimization,'' Proceedings of 17th International Conference on VLSI Design (VLSID), January 2004, Page(s): 713 - 716.

27. S. Alupoaei and S. Katkoori, ``Ant Colony Optimization Technique for Macrocell Overlap Removal,'' Proceedings of 17th International Conference on VLSI Design (VLSID), January 2004, Page(s): 963 - 968.

28. S. Gupta and S. Katkoori, ``Intra-Bus Crosstalk Estimation Using Word-Level Statistics,'' Proceedings of 17th International Conference on VLSI Design (VLSID), January 2004, Page(s): 449 - 454.

29. C. Gopalakrishnan and S. Katkoori, ``KnapBind: An Area-Efficient Binding Algorithm for Low-leakage Datapaths,'' Proceedings of 21st International Conference on Computer Design (ICCD), October 2003, Page(s): 430 - 435.

30. C. Gopalakrishnan and S. Katkoori, ``A Fast Hierarchical Leakage Power Simulator for VHDL Structural Descriptions,'' IEEE Computer Society Symposium on VLSI (ISVLSI), February 2003, Page(s): 211-212.

31. H. Li, W. K. Mak, and S. Katkoori, ``An Efficient LUT-Based FPGA Technology Mapping Algorithm for Power Minimization,'' Asia-Pacific Design Automation Conference (ASPDAC), January 2003, Page(s): 353-358. Nominated for Best Paper Award.

32. C. Gopalakrishnan and S. Katkoori, ``Resource Allocation and Binding for Low Leakage Power,'' 16th International Conference on VLSI Design (VLSID), January 2003, Page(s): 297-302.

33. C. Gopalakrishnan and S. Katkoori, ``Behavioral Synthesis of Datapaths with Low Leakage Power,'' IEEE International Symposium on Circuits and Systems (ISCAS), Volume: 4, May 2002, Page(s): 699 -702.

34. S. Gupta and S. Katkoori, ``Force-directed Scheduling for Dynamic Power Optimization,'' IEEE Computer Society Annual Symposium on VLSI (ISVLSI), April 2002, Page(s): 68-73.

35. C. Gopalakrishnan and S. Katkoori, ``Power Optimization using Input Transformations,'' First IEEE Intl. Workshop on Electronic Design, Test, & Applications (DELTA), January 2002, Page(s): 154-158.

36. S. Alupoaei and S. Katkoori, ``Net Clustering Based Macro-cell Placement,'' 15th International Conference on VLSI Design (VLSID), January 2002, Page(s): 399-404.

37. H. Li, W. K. Mak, S. Katkoori, ``Low Power Mapping for FPGAs with Optimal Depth,'' IEEE Computer Society Workshop on VLSI (WVLSI), April 2001, Page(s): 123-128.

38. S. Katkoori and S. Alupoaei, ``RT-level Interconnect Optimization in DSM Regime,'' IEEE Computer Society Workshop on VLSI (WVLSI), April 2000, Page(s): 143-148.

39. S. Katkoori and R. Vemuri, ``Scheduling for Low Power under Resource and Latency Constraints,'' International Symposium on Circuits and Systems (ISCAS), May 2000, Vol. 2, Page(s): 53-56.

40. A. Durbha and S. Katkoori, ``Route-and-Place Design Methodology for Interconnect Optimization in DSM Regime,'' X IFIP International Conference on Very Large Scale Integration (IFIP VLSI), December 1999, Page(s): 427-438.

41. P. Maurer, S. Katkoori, W. Mak, M. Varanasi, ``Component-Level Programming: A Revolution in Software Technology,'' Proceedings of the Frontiers in Education Conference, Proceedings of the 29th Annual Frontiers in Education Conference, Volume 2, November 1999, Page(s): 12B1/11 -12B1/15.

42. S. Katkoori and R. Vemuri, ``Accurate Resource Estimation Algorithms for Behavioral Synthesis,'' Great Lakes Symposium on VLSI Conference (GLSVLSI), March 1999, Page(s): 338-339.

43. V. Natesan, A. Gupta, S. Katkoori, D. Bhatia, and R. Vemuri, ``A Constructive Method for Data Path Area Estimation During High-Level VLSI Synthesis,'' Asia and South-Pacific Design Automation Conference (ASPDAC), January 1997, Page(s): 509 - 515.

44. S. Katkoori and R. Vemuri, ``Simulation Based Architectural Power Estimation for PLA-Based Controllers," International Symposium on Low Power and Electronic Design (ISLPED), August 1996, Page(s): 121-124.

45. S. Katkoori, J. Roy, and R. Vemuri, ``A Hierarchical Register Optimization Algorithm for Behavioral Synthesis,'' 9th International Conference on VLSI Design (VLSID), January 1996, Page(s): 126-134.

46. S. Katkoori and R. Vemuri, ``A Power Simulator for VHDL Structural Descriptions,'' VHDL International User's Forum (VIUF) Fall Conference, October 1995, Page(s): 4.17-4.25.

47. S. Katkoori, N. Kumar and R. Vemuri, ``High Level Profiling Based Low Power Synthesis Technique,'' International Conference on Computer Design (ICCD), October 1995, Page(s): 446-452.

48. S. Katkoori, N. Kumar, L. Rader and R. Vemuri, ``A Profile Driven Approach for Low Power Synthesis,'' IFIP Intl. Conference on VLSI Design (VLSID), August 1995, Page(s): 759-765.

49. D. Bhatia, R. Rajagopalan, and S. Katkoori, ``Hierarchical Reconfiguration of VLSI/WSI Arrays,'' 7th International Conference on VLSI Design (VLSID), January 1994, Page(s): 349-352.

Peer-reviewed Extended Abstracts

1. S. Katkoori, P. Fernando, H. Sankaran, A. Stoica D. Keymeulen, and R. Zebulum, "Programmable Genetic Algorithm IP Core for Sensing and Surveillance Applications," SPIE 2009 Conference, 13-17th April 2009, Orlando.

2. A. Mast, J. Montealegre, L. Jenkins, S. Katkoori, A. White, and C. Kimmery, "A High-Level Tool for Bit-level SEU Sensitivity Analysis in DSP Filters, Military and Aerospace Applications of Progg. Devices and Technologies (MAPLD), September 2008, Baltimore, Maryland. Publication from a senior project.
   Online Proceedings: http://nepp.nasa.gov/mapld_2008/presentations/wednesday.html

3. S. Katkoori, A. Stoica, D. Keymeulen, R. Zebulum, and R. Ramesham, Field Programmable Gate Arrays (FPGAs) in Extreme Environments - A Survey, IMAPS 2nd Adv. Tech. Workshop on Reliability of Adv. Electronics in Extreme Cold Environments, February 2007, Pasadena, CA.

4. S. Kakarla and S. Katkoori, ``Partial Evaluation Based Redundancy for SEU Mitigation in Combinational Circuits,'' Military and Aerospace Applications of Progg. Devices and Technologies (MAPLD), September 2005.
   Online Proceedings: http://klabs.org/mapld05/abstracts/index.html

5. P. Samudrala, J. Ramos, and S. Katkoori, ``Selective Triple Modular Redundancy for SEU Mitigation in FPGAs,'' Military and Aerospace Applications of Progg. Devices and Technologies (MAPLD), September 2003.
   Online Proceedings: http://klabs.org/richcontent/MAPLDCon03/abstracts/samudrala_a.pdf

ADMINISTRATIVE SERVICES TO UNIVERSITY

• Member, USF Tampa Technology Fee Advisory Council, 2010-2012.

• Chair, USF CoE Outstanding Undergraduate Teaching Award Committee, 2010-2011.

• CSE Department Representative, USF CoE Faculty Governance Committee, 2011-2014.

• CoE Senator, USF Senate, 2010-2013.

• CoE Representative, USF Council on Educational Policies and Issues, 2010-2013.

• CoE Representative, USF Honors and Awards Council, 2010-2013.

• Member, CSE Graduate Committee, 2009-2010.

• Member, Planning & External Relations Committee, 2009-2010.

• Departmental representative, Inaugural CoE Eminent Lecture Series, Spring 2009.

• Graduate Program Director, Computer Science & Engg., May 2006-April 2009.

• Departmental Co-ordinator, Alfred P. Sloan Program, CoE, USF, May 2006-Dec 2008.

• College Grievance Committee, Summer 2006 (Chair), Spring 2009 (Member).

• Departmental Tenure & Promotion Committee, 2004-present.

• Graduate Admissions Co-ordinator, 2004-2005.

• Member, Graduate Admissions Committee, 2003-2009.

• Member, Departmental Infrastructure Committee, 2003-present.

• Supervisor for the Departmental Technical Support 1999-2003.

• Departmental representative on the Safety and Health Committee 2000-present.

• Departmental representative on the interdepartmental committee on Packaging 1998-99.

• Departmental library representative 1998-2001.

• 1998/99 Departmental representative to Graduation.

• MS Comprehensive and PhD Qualifiers Examination Committee, Computer Architecture Section (Fall & Spring Semesters, 1997-present).

• MS Comprehensive and PhD Qualifiers Examination Committee, Member of the sub-committee on the Advanced Digital Systems (ADS)(Fall 1998, Spring 1999).

• On the undergraduate curriculum evaluation committee for planning, development, and evaluation of computer engineering program (Fall 1997).

SERVICE TO PROFESSION

Journals

• Associate Editor, IEEE Transactions on VLSI Systems, Nov 2006 - present.
• Reviewer, IEEE Transactions on Computer-Aided Design of ICs and Systems.
• Reviewer, IEEE Transactions on Computers.
• Reviewer, IEEE Transactions on Evolutionary Computation.
• Reviewer, IEEE Transactions on VLSI Systems.
• Reviewer, ACM Transactions on Design Automation of Electronic Systems (TODAES).
• Reviewer, Journal on Low Power Electronics (JOLPE).
• Reviewer, Journal of Intelligent and Robotic Systems.
• Reviewer, Journal on VLSI Signal Processing Systems.
• Reviewer, Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3).
• Reviewer, IEE Proceedings on Computers & Digital Techniques.
• Reviewer, The Computer Journal.
• Reviewer, Integration, the VLSI Journal.

Conferences

• General Co-chair & Registration Chair, 2001 IEEECS Workshop on VLSI, Orlando, FL.
• Registration & Publicity Chair, 2000 IEEECS Workshop on VLSI, Orlando, FL.
• Local Arrangements Chair, 2009 Intl. Symposium VLSI 2009, Tampa, FL.
• Session Chair, IMAPS 2007 Workshop on Extreme Cold Electronics
• Session Chair, ``Synthesis,'' 1999 Great Lakes Symposium on VLSI (GLSVLSI)
• Session Chair, ``Low Power Design,'' 2008 International Conference on VLSI Design
• TPC Member, Intl. Symposium on Quality of Electronic Design (ISQED) 2006, 2008
• TPC Member, IEEE Computer Society Symposium on VLSI (ISVLSI)
• TPC Member, Intl. Conference on Computer Design (ICCD)
• TPC Member, Reconfigurable Architectures Workshop (RAW), (Years: 2005, 2008)
• TPC Member, Field Programmable Logic (FPL), 2008,
• TPC Member, IFIP VLSI System-on-a-Chip (SOC) Conference
• TPC Member, Asian Symposium on Quality of Electronic Design (ASQED)
• TPC Member, IEEE SOC Conference, Portland, OR, 2003.
• Reviewer, Micro-electronics System Education (MSE), 2007
• Reviewer, Design Automation Conference (DAC), 2008
• Reviewer, Military and Aerospace Programmable Logic Devices (MAPLD), 2005
• Reviewer, Intl. Syposium on Circuit and Systems (ISCAS)
• Reviewer, Midwest Symposium on Circuit and Systems (MWSCAS) 2008
• Reviewer, Intl. Conf. on Embedded Software and Systems (ICESS) 2007
• Reviewer, Intl. Conf. on VLSI Design, 2008
• Reviewer, IEEE System on a Chip (SOC) Conference
• Reviewer, Adaptive Hardware Systems AHS 2006
• Reviewer, NSF SBIR Panel, 2003.
• Reviewer, DAC PhD Forum, 2004
• Reviewer, International Conference on Computer Design (ICCD), 2004

Other Service

• Lecturer, 2011 ACM SIGDA Design Automation Summer School (DASS).
• General co-chair, 2011 ACM Student Research Competition.
• Treasurer, ACM SIGDA, Fall 2010 - present.
• Board Member, ACM SIGDA Fall 2010 - present..
• Publicity Chair and Organizing Member, ACM Cadathlon Contest, Nov. 2009.
• IEEE Senior Member Review Panel, Tampa, FL, Spring 2009.
• Judge, USF Research Day, Engineering Research Poster Contest, Spring 2009.
• Mentor, Undergraduate Research Competition, Spring 2008.
• Editor-in-Chief, The Suncoast Signal, IEEE Florida West Coast Section (FWCS) Monthly Newsletter,
• Judge, USF EE Senior Project Poster Competition, Fall 2006.
• Faculty Advisor, USF IEEE Computer Society Student Chapter 1999-2005.
• Mentor, Research Experiences for Teachers (RET), Summer 2004.
• Proposal Reviewer, Florida I4 High Tech Corridor Grant Program, Summer 2004.

GRADUATE THESIS/DISSERTATION COMMITTEES

PhD Dissertation Committee Member

At USF:

1. Madhusmita Behera, Moffitt Cancer Center (Advisor: Dr. John Hines), USF
2. Jorge Galvis (Advisor: Dr. Wilfredo Moreno, EE, USF)
3. Alberto Rodriguez (Advisor: Dr. Tom Weller, EE, USF)
4. Upavan Gupta (Advisor: Dr. N. Ranganathan, CSE, USF), Summer 2008
5. Ashok Murugavel (Advisor: Dr. N. Ranganathan, CSE, USF), Spring 2003
6. Koustav Bhattacharya (Advisor: Dr. N. Ranganathan, CSE, USF), Fall 2009
7. Mahalingam Venkataraman (Advisor: Dr. N. Ranganathan, CSE, USF), Spring 2009
8. Sanjukta Bhanja (Advisor: Dr. N. Ranganathan, CSE, USF), Fall 2002
9. Thara Rejimon (Advisor: Dr. Sanjuktha Bhanja, EE, USF),
10. Saraju Mohanty (Advisor: Dr. N. Ranganathan, CSE, USF), Fall 2003
11. David Aguilar (Advisor: Dr. Rafael Perez), Fall 2007
12. Elizabeth Horton (Advisor: Dr. N. Ranganathan, CSE, USF)

Outside USF:

1. Jawad Khan, ECECS, Univ. of Cincinnati (Advisor: Dr. Ranga Vemuri)
2. Xin Jia, ECECS, Univ. of Cincinnati (Advisor: Dr. Ranga Vemuri)
3. Shubhankar Basu (Advisor: Dr. Ranga Vemuri, ECECS, Univ. of Cincinnati), Spring 2008
4. Madhubanthi Mukherjee, ECECS, Univ. of Cincinnati (Advisor: Dr. Ranga Vemuri)
5. Manish Handa, (Advisor: Dr. Ranga Vemuri, ECECS, Univ. of Cincinnati),
6. Preetham Lakshmikanthan (Advisor: Dr. Adrian Nunez, ECE, Syracuse University)

MS Thesis Committee Member

1. Brian Hayes, CSE (Advisor: Dr. Ranganathan),
2. Vasanth Ramesh, CSE (Advisor: Dr. Ranganathan),
3. Ryan Mabry (Advisor(s): Dr. N. Ranganathan and Dr. H. Zheng) Defended in Summer 2007.
4. Shankar Arumuguvelu (Advisor: Dr. N. Ranganathan) Defended in Summer 2007.
5. Alejandro G. Munoz (Advisor(s): Dr. Larry Hall and Dr. D. Goldgof), Fall 2008.
6. Zornitza Genova (Advisor: Dr. Martha Escobar Moleno)
7. Arun Solleti (Advisor: Dr. Ken Christensen)
8. Jared Ahrens, (Advisor: Dr. Hao Zheng)
9. Khalid N. Hamzan, (Advisor: Dr. Peter Maurer)
10. Rohini K. Jella, (Advisor: Dr. Dewey Rundus)
11. Praveen Ikkurthy (Advisor: Dr. Miguel Labrador)
12. Subodh Kerkar (Advisor: Dr. Miguel Labrador)
13. Vipul Mistry (Advisor: Dr. Murali Varanasi)
14. Sunil Chappidi (Advisor: Dr. N. Ranganathan)
15. Sivakumar Bakthavachalu (Advisor: Dr. Miguel Labrador)
16. Alejandro G. Munoz (Advisor: Dr. Larry Hall)
17. Joshua Johnson (Advisor: Dr. Eugene Fink)
18. Srinath Chavali (Advisor: Dr. N. Ranganathan)
19. Mohammed Gharawi (Advisor: Dr. Peter Maurer)
20. Karthikeyan Balakrishnan (Advisor: Dr. N. Ranganathan)

PhD Dissertation Defense Chair

At University of South Florida, the Graduate School requires the PhD defense to be chaired by a Professor outside the candidate's department.

1. Bhaskar Tetali, EE (Advisor: Dr. Chris Ferrikides), Spring 2005
2. Balaji Lakshminarayanan, EE (Advisor: Dr. Tom Weller), Fall 2005
3. Charles Baylis (Advisor(s): Dr. Larry Dunleavy and Dr. Dave Snider, EE, USF), Spring 2007
4. Son Ho (Advisor: Dr. Muhammad Rahman, MechE, USF), Summer 2007
5. Saravana Natarajan (Advisor: Dr. Tom Weller, EE, USF), Fall 2007
6. Sathyaharish Jeedigunta, EE, USF (Advisor(s): Dr. Ashok Kumar, MechE, and Dr. Shekhar Bansali, EE), Spring 2008
7. Subramanian Krishnan, EE, USF (Advisors: Dr. Shekhar Bhansali, EE, and Dr. Lee Stefanakos, EE), Spring 2008
8. Carlos L. Castillo (Advisors: Dr. Wilfredo Moreno, EE, and Dr. Kimon Valavanis, CSE), Spring 2008