CIS 6930
		Grad Topics: Low Power CMOS VLSI Design and CAD
			  Fall 1998; MW 12:30-1:45 pm

 Instructor: Dr. Srinivas Katkoori
	    Office: ENB 316	    Office Hours: MW 10-11:30 am
	    Phone:  974-5737	    Email:	  katkoori@csee.usf.edu

 Teaching Assistant: TBA

 Webpage: http://www.csee.usf.edu/~katkoori/courses/cis6930/cis6930_fall98.html

 Prerequisites:
 Basic CMOS VLSI Design course or an equivalent course approved by the instructor.

 Background & Motivation:
 Excessive power dissipation in modern microprocessors and limited power budget 
 for high performance portable electronics have underlined the need for low 
 power VLSI design methodologies.  Power minimization enables the usage of 
 inexpensive packages (thus reducing overall cost), increases chip reliability 
 and life-time. In last five to six years copious low power techniques 
 have been developed at all levels of design abstractions, namely, layout, 
 gate-level, RTL, behavioral, and system-level.  We will study these 
 techniques in detail.

 Objectives: To make the student a {\em power-conscious} VLSI designer -- is the 
 sole objective of this course. It will be achieved by: low power design 
 exercises (using MAGIC, SPICE, IRSIM, and other state-of-the-art CAD tools),
 an extensive literature survey, and a project (involves implementing a popular 
 low power CAD algorithm in C/C++).

 Outline:
  o Review of CMOS technology and VLSI design styles (5 hrs);
  o Power consumption in CMOS circuits (3 hrs);
  o Power estimation techniques at layout, logic, 
 	RTL, and behavioral levels (10 hrs);
  o Power optimization techniques at layout, logic, 
 	RTL, and behavioral levels (12 hrs);
  o A typical design flow for system-level power minimization (4 hrs);
  o Asynchronous \& Adiabatic techniques for low power(3 hrs);
  o Conclusions (2 hrs)

 Class Notes: Available via course homepage. 

 Bibliography

 (1) ``CMOS Low Power Digital Design,'' A. Chandrakasan \& R. Brodersen, 
      Kluwer Academic Pubs., 1995.
 (2) ``Low Power Design Methodologies,'' J. Rabaey \& M. Pedram (Editors), 
      Kluwer Academic Pubs., 1996.
 (3) ``Low Power Design in Deep Submicron Electronics,''	Edited by 
      W. Nebel \& J. Mermet, NATO ASI Series, Kluwer Academic Pubs., 1997.  
 (4) ``Computer-Aided Design Techniques for Low Power Sequential Logic Circuits,'' 
     J. Monteiro \& S. Devadas, Kluwer Academic Publishers, 1997. 
 (5) ``Logic Synthesis for Low Power VLSI Designs,'' S. Iman \& M. Pedram,
     Kluwer Academic Pubs., 1998. 
 (6) ``Principles of CMOS VLSI Design: A Systems Perspective,'' N. Weste \& K. Eshragian,
     Addison-Wesley, 1985.	
 (7) Proceedings of International Symposium on Low Power Electronic Design (ISLPED), 
     1994--1997.

 Grade Distbn: 	Homeworks:  25%
	   	Midterm:    25%
		Term Paper: 25%
		Project:    25%

 Grading Policy: A - 90%   B - 80%	C - 70%    D - 60%	F - Less than 60%

 General Policies:

 o One midterm will be conducted.  The date for the midterm will 
   be announced in the class.

 o Academic dishonesty will not be tolerated and the student, 
   in question, will be dealt with in accordance to the University policies.

 o If you need any special accomadation according to the American 
   Disability Act, please let me know.

 o Students who anticipate the necessity of being absent from class due to the 
   observation of a major religious observance must provide notice of the date(s) 
   in writing by the second class meeting.


					Good Luck !!